China's chip design bottleneck is software, and it is closing slowly

Discussion of China's semiconductor position usually starts at the fab. The more binding constraint sits earlier in the chain, in the software used to design chips at all — and it is the clearest illustration of how export controls actually work in practice, which is to say unevenly.

Where the foreign tools still hold

Electronic design automation for 7nm and below in China remains dominated by Synopsys, Cadence and Siemens EDA. Their advantage is not any single tool but full-flow coverage: digital design, verification and physical implementation, integrated deeply with global foundry process design kits. At 3nm and 2nm GAAFET design, and in advanced verification methodology, that lead remains substantial.

Foundry dependency is what makes this sticky. EDA tools are bound tightly to the PDKs of the fabs that will manufacture the design. A tool that cannot talk to a continuously updated production process is not much use, whatever its licence status.

Where domestic substitution has genuinely arrived

The progress is real, and it is concentrated in specific places.

Empyrean has achieved full-flow analogue circuit EDA coverage — analogue, RF and memory — with a validated 14nm digital flow and 7nm certification in progress. Its ALPS circuit simulation tool holds 8nm, 5nm and 4nm advanced process certifications. It has become the foundation of the domestic EDA base.

Huawei launched a full-flow self-developed toolchain covering its entire chip design process. Primarius, X-Epic and VeriSilicon specialise respectively in device modelling, verification and FPGA design tools.

Domestic tools are usable in digital front-end design, logic synthesis and static timing analysis. On 10 May, TSMC opened its 7nm+ EDA tool certification APIs to five Chinese EDA companies, streamlining PDK compatibility validation. Nineteen joint laboratories now link domestic EDA firms with SMIC, YMTC and JCET.

The gap that matters is hardware emulation and functional verification — the areas decisive for ultra-large-scale chip design, and where the distance from international leaders remains significant. A design house can synthesise a chip with domestic tools and still be unable to verify it at scale.

The structural weaknesses compound: domestic vendors exist mostly as point tools with fragmented capability and no unified data foundation across the flow, producing a broken design process. And the talent pool is thin — the total number of domestic EDA developers is roughly a third to a quarter of the international majors'.

What the controls have actually achieved

Tools supporting GAAFET at 3nm and 2nm remain under strict export control. The US Bureau of Industry and Security briefly required the three major vendors to suspend exports to China; that was lifted in July 2025 for most mature-process tools.

Several things followed, and they are worth stating plainly as analysis rather than advice.

Companies that bought perpetual licences before restrictions took effect continued using them without updates or technical support — a real short-term buffer for design continuity, and a wasting one, since processes below 5nm iterate. International vendors have released feature-reduced versions for the Chinese market, stripping GAAFET support while retaining FinFET and legacy flows, in order to hold market share. And engineering effort has redirected toward chiplet architectures, integrating multiple mature-node dies through advanced 2.5D and 3D packaging to reach system-level performance without advanced-node design tools.

There are also arrangements that sit outside compliance — third-country purchasing structures and remote access to tools hosted on overseas servers. These carry rising risk as BIS strengthens knowledge-standard reviews and corporate compliance obligations, and they run into the same foundry problem: unauthorised software cannot follow a production process that keeps moving.

The author's own assessment is the right conclusion to draw: these are stopgaps. The durable answer, from Beijing's point of view, is substitution — which is why Empyrean has offered free trials to domestic users to accelerate switching, and why a ¥5 billion national EDA industry guidance fund is planned under the 15th Five-Year Plan.

Read that way, the controls have not stopped Chinese chip design. They have set its ceiling, bought time, and made domestic substitution a national priority with a funded timeline.

The edge inference market tells a different story

The GPU picture at the edge is instructive precisely because it is not a story of exclusion.

Nvidia's Orin and Jetson lines sit below the BIS performance threshold — total processing performance under 21,000 — and remain eligible for case-by-case licence review. Developer kits and production modules are available through authorised distributors, though lead times have lengthened. Jetson Thor is exportable, with stricter scrutiny for potential military end use.

The resulting split is stark. Nvidia's data centre GPU share in China has collapsed to around 8%. Its edge GPU share remains roughly 45% for high-performance applications. Imported Orin and Jetson modules carry a 25–45% price premium against global markets, reflecting supply uncertainty and inventory hoarding — Chinese firms built six to nine months of stock in 2025, now depleting as domestic alternatives improve.

Where substitution has bitten:

• Automotive — Orin-X remains the benchmark for L2++/L3 systems and is still used in legacy models and by international automakers operating in China, but monthly installations are declining. Orin-N has been almost entirely displaced in the mid-range. NIO's Shenji NX9031 at 5nm and 1,000 TOPS powers 82% of new NIO models; Horizon's J6 series ranks third overall; XPeng's Turing chip at 750 TOPS powers the G9 and P7i; BYD's 4nm Xuanji A3 is going into the Dynasty and Ocean series.
• Robotics and industrial — Jetson remains the standard. Orin NX is the most popular module for industrial robots and AGVs; Orin Nano dominates smart cameras and edge sensors; AGX Thor has been adopted by Unitree, UBTECH and Fourier Intelligence. Domestic alternatives — Huawei Ascend 310B, Horizon Journey 5, Black Sesame Huashan-2 — are taking government, collaborative robot and logistics applications.
• Government — 92% of new deployments use domestic chips, primarily Huawei Ascend 310B and Cambricon MLU220. Nvidia Jetson still holds around 55% in the private sector on software ecosystem and developer support.

The Cyberspace Administration has mandated domestic AI chips in state-funded new data centres and instructed Alibaba and ByteDance to suspend testing and cancel orders for the China-specific RTX Pro 6000D.

Substitution moves fastest where absolute compute matters least and supply security matters most. It is slowest where the software ecosystem is the product.

What this means if you are on the European side

Distinguish design software from manufacturing when assessing a Chinese partner. A firm using domestic analogue EDA at mature nodes has a durable, compliant tool position. A firm dependent on unsupported perpetual licences for sub-5nm work is running on a depleting asset. These are very different risk profiles that look identical from outside.

Chiplet and advanced packaging is where the engineering effort has gone. If controls push Chinese design toward integrating mature-node dies, then packaging, substrates, thermal management and interconnect become the areas of fastest capability growth — and the most likely places to find both partners and competitors.

Edge AI is an open market with a closing window. Current edge GPUs remain exportable, but the direction of travel in both capitals is restrictive, and domestic substitution accelerates each time a threshold moves. Commercial relationships in this segment should be structured for that, not against it.

The honest summary from the Chinese side is that high-end AI training will depend on top international products for a long time yet. The compiler optimisation and model porting work now underway is aimed squarely at that dependency, and chiplet design at the process-node limits. Neither problem gets solved quickly, and both are being worked on with a funded plan.