China's AI chip problem is not the silicon, it is CUDA

Discussion of Chinese AI compute usually asks whether domestic chips can match NVIDIA's. The more revealing question is what happens when they nearly do, because the answer exposes where the actual dependency sits — and it is not in the hardware.

The hardware gap is narrower than assumed

Huawei's Ascend 910B delivers roughly 40–60% of an NVIDIA H100's compute at about 60% of the cost. More striking is what happens at cluster level: the CloudMatrix 384 supernode, built from 384 Ascend 910C chips, delivers 300 PFlops of BF16 performance — exceeding NVIDIA's GB200 NVL72 in total throughput.

It consumes 3.9 times the power to do it.

That trade is the whole strategy in one number. Where energy is comparatively cheap and chips are constrained, spending power to compensate for per-chip performance is rational. It is not a workaround; it is an engineering response to the specific constraint China faces, and it works for training workloads where total throughput matters more than efficiency.

Elsewhere: Lightelligence's PACE photonic chip solves combinatorial optimisation roughly ten times faster than comparable NVIDIA parts, though only for specific workloads. Tencent has deployed Suiyuan's Susi 3.0 in speech recognition and recommendation, reporting training speeds twice those of conventional GPU clusters. And DeepSeek has reduced training costs by around 75% through algorithmic optimisation rather than hardware.

The software gap is the real one

NVIDIA's CUDA ecosystem has over three million developers. That is the moat, and it is not narrowing quickly.

Huawei's CANN platform achieves around 70% CUDA code compatibility and holds 70.8% of China's AI server market, supporting PyTorch and ONNX, with Atlas servers reportedly achieving 75% lower training costs in cloud environments. Moore Threads' MUSA 4 SDK provides CUDA-like tooling across x86, ARM and Loongson.

But CANN's operator coverage is around 60%, against CUDA's 95%. CUDA-X libraries — cuDNN, TensorRT — offer optimisation that Chinese alternatives have not replicated. Domestic frameworks like Huawei's MindSpore and Baidu's PaddlePaddle are building ecosystems from a standing start against a fifteen-year head start.

Seventy per cent code compatibility sounds close. In practice it means the remaining 30% is where the hard, performance-critical work lives, and every model port pays that cost again.

Where semiconductor autonomy actually stands

The picture is one of genuine progress at mature nodes and persistent dependency at the frontier.

Achieved: SMIC's 14nm yield is around 75%. YMTC's 232-layer 3D NAND reaches 92% yield. A domestic 28nm lithography tool, the SSA800, is operational. Semiconductor imports fell from 79% to 68% of total demand between 2020 and 2025, with roughly $300 billion invested since 2018.

Not achieved:

• Equipment — only around 15% of semiconductor manufacturing equipment is domestically produced. Lithography, etching and deposition remain import-dependent, though domestic production is projected to rise from 7% in 2018 to 22% by 2025, with Naura reportedly achieving 92% yield on etching tools
• EDA — dependency on Synopsys and Cadence persists
• Advanced packaging — China lags in chiplet and 3D integration, both critical to AI chip performance, with foreign suppliers dominating thinning and bonding tools
• Materials — high-purity silicon carbide and EUV photoresist are still imported, with domestic alternatives at roughly 60% of international quality
• Advanced nodes — SMIC plans to quadruple 7nm capacity, with yields reported around 20% against TSMC's 85%, attributed to photoresist impurities and inconsistent etching

The materials and yield numbers are the ones to watch. A 20% yield at 7nm is not a production process; it is a research programme with a fab attached. Closing it depends on photoresist purity, which depends on materials capability, which is the least visible and slowest-moving part of the chain.

On reverse engineering

The source material discusses reverse engineering as a route around equipment restrictions, and it is worth treating carefully — both because the claims vary in how well established they are, and because the practice is legally contested.

What is documented: SMEE's 28nm DUV tool incorporates a thermal compensation approach derived from studying ASML equipment, achieving 0.03μm accuracy, and its EUV prototype uses LDP technology. YMTC's 232-layer design followed close study of existing 3D NAND architectures, with yield and endurance still behind Samsung's 176-layer parts.

Claims that specific Chinese AI accelerators are derived from teardowns of restricted NVIDIA parts circulate in industry analysis but rest on architectural resemblance rather than evidence, and should be treated as assessment rather than fact.

The constraints on the approach are severe regardless. EUV lithography requires over 100,000 components, of which China produces around 45% domestically — you cannot reverse-engineer a supply chain. Reverse-engineered designs carry patent exposure. And yield, which is where process knowledge rather than design lives, does not transfer by inspection.

Reverse engineering has compressed the timeline at mature nodes. It has not solved the frontier, and the reasons it has not are structural.

What this means if you are on the European side

Ecosystem lock-in is the durable asset, and Europe has none. The lesson of CUDA is that fifteen years of developer tooling outlasts any particular chip generation. European AI hardware efforts that focus on silicon without the software layer are competing on the dimension that matters least.

Materials and metrology are where European leverage is real. High-purity photoresist, silicon carbide and precision metrology are the constraints holding Chinese advanced-node yields at 20%. That is a narrow, high-value position — and it is exactly the position that export control policy makes commercially precarious, so it needs deliberate strategy rather than drift.

Assume Chinese AI compute will be adequate and cheap, not excellent. Between cluster-scale compensation, algorithmic efficiency work and a 60%-cost position, the practical outcome for most commercial workloads is sufficient capability at low price. Strategies premised on Chinese firms being compute-constrained are betting against three separate workarounds at once.

The gap that will persist longest is not the chip. It is the three million developers, the operator coverage, and the fifteen years of accumulated optimisation that sit between a working accelerator and one people choose to use.